Labs

Lab Number	Lab Description
	Sample Lab Report to Serve as a Model. It also shows how to incorporate a low-level design into a higher-level design using packages and component declarations. VHDL Reference Manual VHDL Reference (Appendix A of Brown & Vranesic)
1	VHDL for Combinational Logic Example lab report for this assignment
2	VHDL for Sequential Logic
3	VHDL for State Machines
4	SRC One-bus Documentation of the Minimal SRC One-Bus Implementation Source Files Output Waveform (568 kB) Instructions on how to use the Final Test Program Final Test Program
5	Pipelined SRC Documentation of the Minimal Pipelined SRC Implementation Source Files
6	Pipelined SRC with Interrupts