EE362 Computer Architecture Lab


Lab # 



VHDL Revisited
Sample Lab Report to Serve as Model.  It also shows how to incorporate a low-level design into a higher-level design using packages and component declarations.

Waveforms for functional simulation of Part (a).  Signals a, b, c, and d are the inputs; signal f is the output.  These waveforms show the results of a functional simulation without regard to timing.  There is nothing here to suggest that the output waveform cannot respond instantly to changes in the input.

Waveforms for timing simulation of Part (a).  Signals a, b, c, and d are the inputs; signal f is the output.  These waveforms show the results of a simulation of both the logic and the timing.  The target FPGA here is the Altera Flex 10K, model EPF10K70RC240-4.  Note that the input waveforms are stable for a much longer time than the functional simulation suggested was required.  A timing analysis of the circuit indicated that the delay from any input to the output was around 19.9 ns.  The input waveforms were therefore made to be stable for roughly twice as long as this so that outputs would change in the middle of each segment of the input waveforms.  You should always conduct such a timing analysis to avoid driving your circuits too fast.
A Ripple-carry Adder
SRC One-Bus
Documentation of the Minimal SRC One-Bus Implementation
Source Files
Waveform Generated by the Test Program SRCProgram1.mif
SRC One-Bus:  Extension



A Sample of a Hierarchical Design in VHDL AlteraFiles.zip (167 kB)  Download and unzip all the Altera Quartus II design files into a directory.  Then open them using Quartus II.
Description of how to use the hierarchical files.
mydff.vhd 
A one-bit D-flip-flop
mydff.vwf
A simulated waveform file to show a test of mydff.vhd.
cameronpkg.vhd
A package to hold low-level designs.  In particular, it holds mydff.vhd and dreg.vhd.
dreg.vhd
An N-bit register built using mydff.vhd.
dreg.vwf
A simulated waveform file to show a test of dreg.vhd.
dreg_n.vhd
A 16-bit register using dreg.vhd and the generic parameter N=16.
dreg_n.vwf 
A simulated waveform file to show a test of dreg_n.vhd.


Example of an N-bit shift register. ShiftRegisterReport.pdf