United States Naval Academy
Department of Electrical and Computer Engineering
EE485F: Superscalar Processor Design
Section 3001
Fall 2010
Course Description
Course Policy
(including specification of textbook.)
Syllabus
Lesson slides
Homework Assignments and Solutions
Additional Problems
Contacting the Instructor
Information About the Term Paper
Schedule for Student Presentations
Grading rubric for the oral presentation
Standard Performance Evaluation Corporation (SPEC)
Simulation of MESI cache protocol
Write-through cache simulation
Point of contact :
CAPT Charles B. Cameron, USN
Revision date :
URL: