Recent improvements in the memory capacity of Field
Programmable Gate Arrays (FPGAs) have spurred interest
in using the devices for arithmetic floating-point operations.
However, adapting a program designed to run on a sequential
processor to be run instead on an FPGA can be timeconsuming
and difficult for anyone lacking significant experience
in hardware design. In this paper we use a high-level
language (HLL)—Mitrion-C 1.4—to reduce some of
this
effort. Using this language we implemented on an FPGA
two computations taken from a ray-tracing simulation. They
were functionally identical to programs we implemented on
a sequential processor. We measured throughput and power
consumption for both implementations of each computation
on a Cray-XD1 system. In the worst case, we achieved a
10× speedup using FPGAs over sequential processors at a
cost of 1.3× the power.